In many electronic circuits, it is necessary to generate internal clocks with predetermined phase relationships to a reference clock. Clock synchronization circuits such as phase locked loops (PLLs) or delay locked loops (DLLs) are often used to generate an internal clock signal that is synchronized, or in phase, with a reference clock signal. FIG. 1 is a functional block diagram of a conventional DLL 100. The DLL 100 includes a voltage controlled delay line (VCDL) 104 that receives a reference clock (RCLK) signal, and in response, generates a delayed clock (DELCLK) signal having a delay relative to the RCLK signal that is based on a voltage of a voltage control (VCTRL) signal. The DLL 100 also includes a phase detector (PD) 108 that receives the RCLK and DELCLK signals and generates UP and DN control signals. The respective values of the UP and DN signals depend on the phase difference between the RCLK and DELCLK signals. For example, if the DELCLK signal leads the RCLK signal, the DN signal goes high and remains high until the next rising edge of the RCLK signal, while the UP signal remains low. If the DELCLK signal lags the RCLK signal, the UP signal goes high and remains high until the next rising edge of the DELCLK signal, while the DN signal remains low. A delay controller 112 generates the VCTRL signal in response to the UP and DN signals from the PD 108. In operation, the delay controller 112 applies the VCTRL signal to the VCDL 104 to adjust the variable delay of the VCDL 104 until the RCLK and DELCLK signals are in phase, as detected by the PD 108. Under this condition, the DLL 100 is referred to as being “locked.”
A bias generator 116 included in the DLL 100 applies a constant BIAS signal to the delay controller 112 and is coupled to the PD 108 to disable it during initialization of the DLL 100. During power-up or reset of the DLL 100, the PD 108 is disabled by the bias generator 116 by, for example, through the use of an active DISABLE signal. When the PD 108 is disabled, the delay controller 112 generates the VCTRL signal in response to the BIAS signal provided by the bias generator 116. The BIAS signal has a constant voltage that is used by the delay controller 112 to set an initial voltage for the VCTRL signal applied to the VCDL 104. In response, the VCDL 104 generates a DELCLK signal having an initial delay set by the voltage of the VCTRL signal. After the start-up or reset, and the DLL 100 has been initialized, the BIAS signal is no longer provided to the delay controller 112 and the PD 108 is enabled by the bias generator 116. Following initialization, the DLL 100 operates as previously described.
FIG. 2 shows various signals generated during power-up and thereafter by the DLL 100. Shortly after the DLL 100 is reset, the delay controller 112 generates a VCTRL signal to set an initial delay for the VCDL 104 in response to the bias generator 116 (shown in FIG. 1) applying a BIAS signal having a voltage V1. The VCDL generates the DELCLK#1 signal having an initial delay relative to the RCLK signal. In the example of FIG. 2, the DELCLK#1 signal initially leads the RCLK signal by 240 degrees, corresponding to the voltage of the BIAS signal establishing an initial voltage V1 for the VCTRL signal, which results in an initial delay that creates a 240 degrees phase difference between the DELCLK#1 signal and the RCLK signal.
Next, after the DLL 100 has been initialized, the BIAS signal is removed and the PD 108 is enabled. The PD 108 compares the phase of the DELCLK#1 signal to the phase of the RCLK signal and generates the UP and DN signals accordingly. As will be understood by those skilled in the art, since the DELCLK#1 signal leads the RCLK signal, the PD 108 generates DN#1 signal responsive to the phase difference between the DELCLK#1 and RCLK signals. In response to the DN#1 signal, the delay controller 112 generates the VCTRL signal (not shown) that is used to adjust the phase delay of the DELCLK#1 signal until the phase difference between the DELCLK#1 signal and the RCLK signal is eliminated. As shown in FIG. 2, the phase delay of the DELCLK#1 is increased responsive to the DN#1 signal until the phase difference between the DELCLK#1 signal and the RCLK signal is 360 degrees. When the DLL 100 is locked, the delay between RCLK and DELCLK#1 signal is equal to one clock cycle. In FIG. 2, the PD 108 will force the delay controller to add delay to the DELCLK signal.
FIG. 2 also shows various signals generated when a BIAS signal having a voltage V2 is applied to the delay controller 112, which in turn generates a VCTRL signal having an initial voltage to set an initial delay of the VCDL 104. In response to the VCTRL signal having a voltage set by the voltage V2 of the BIAS signal, the VCDL 104 generates the DELCLK#2 signal that lags the RCLK signal by 30 degrees. Thus, in the example of FIG. 2, the BIAS signal having a voltage V2 results in an initial delay that creates a 30 degrees phase difference between the DELCLK#2 signal and the RCLK signal. As shown in FIG. 2, the phase delay of the DELCLK#2 is increased responsive to the UP#1 signal until the phase difference between the DELCLK#2 signal and the RCLK signal is eliminated by the third cycle. In comparison to the previous example, applying the BIAS signal having a voltage V2 results in the DLL 100 obtaining a lock condition sooner than for of a BIAS signal having a voltage V1.
FIG. 2 illustrates that the amount of time required to eliminate the phase difference between the DELCLK and RCLK signals depends, among others, on the voltage of the BIAS signal applied during initialization of the DLL 100, which in turn is used to establish an initial voltage of the VCTRL signal applied to the VCDL 104 to set an initial delay. Therefore, selecting a voltage for the BIAS signal that reduces the time required to eliminate the phase difference is desirable. If the voltage of the BIAS signal is not selected properly, it may require a relatively long period of time for the DLL 100 to eliminate the phase difference.
Selection of a proper initial bias voltage is also important because of the effects of process variations in semiconductor integrated circuits (ICs). The process variations refer to variations in semiconductor fabrication processing steps such as, for example, ion implantation, deposition, lithography and etching that affect the performance of ICs. Voltage and temperature variations also affects the performance of ICs.
It can be difficult to select a voltage for the BIAS signal that will result in the DLL 100 acquiring lock quickly in every operating condition. For example, the voltage of the BIAS signal may be sufficient to facilitate the DLL 100 quickly acquiring lock under some voltage, temperature, and frequency operating conditions, but given a different set of operating conditions, it may take significantly longer for the DLL 100 to acquire lock. Although it is known that semiconductor devices behave differently under different operating conditions, process variations may cause circuits inside the VCDL 104 to behave significantly different under the different voltage or temperature conditions. The delay stages inside the VCDL 104 may be faster under one set of operating conditions , but may be too slow under another set of operating conditions to pass high speed signals at the specific voltage or at the specific temperature. As illustrated by the present example, given different voltage and temperature operating conditions, the voltage of the BIAS signal that is used to establish the initial voltage of the VCTRL signal applied to the VCDL 104 may be sufficient for one set of operating conditions but insufficient for another.
Typically, the voltage of the BIAS signal is selected to establish the initial voltage of the VCTRL signal applied to the VCDL 104 to set an amount of the variable delay that is approximately 50% of the maximum delay of the VCDL 104. However, the process variations discussed above may cause the variable delay to have an initial delay that is far from the 50% maximum delay condition under some operating conditions. In a case where the process variations have caused a significant shift in operational characteristics of the VCDL 104, the VCDL 104 may fail to generate a DELCLK signal from the RCLK signal for the initial voltage of the VCTRL signal (as established by the BIAS signal) when operating under extreme operating conditions, but are still within the operational corners of variations in Process, Voltage, Temperature and Frequency (PVTF). For example, the VCDL 104 may be unable to generate a DELCLK signal in response to the RCLK signal at slow corners (i.e., slow process, low voltage, high temperature) and high clock frequency. Under these conditions, the output of the VCDL 104 may merely be a dc signal. Consequently, the PD 108 will not be able to compare the phase of the RCLK signal to the phase of the DELCLK signal, and the delay controller 112 will not correctly adjust the variable delay of the VCDL 104 because the UP and DN signals generated by the PD 108 do not accurately represent the phase difference of the DELCLK and RCLK signals.
Accordingly there is a need for a circuit that applies an initial bias voltage in a clock synchronization circuit, such as the DLL 100, that facilitates the rapid adjustment under various operating conditions of a voltage controlled delay circuit to eliminate the phase difference between a reference clock signal and a clock signal generated by the voltage controlled delay circuit in response to the reference clock signal.